Innovation on a Memory Based Multiplier

Several architectures have been reported in the literature for memory-based implementation of DSP algorithms involving orthogonal transforms and digital filters. A common way of implementing constant multiplication is by a series of shift and adds operations. If the multiplier is represented in Canonical Signed Digit (CSD) form, then the number of additions (or subtractions) used will be a minimum by sharing the two most common sub expressions which can be expected to lead to a 33% saving of the number of additions. The multiplier uses look-up-table (LUT) as memory for their computations. However, we do not find any significant work on LUT optimization for memory-based multiplication. A new approach to LUT design was presented, where only the odd multiples of the fixed coefficient are required to be stored which we have referred to as the odd-multiple storage (OMS) scheme. In addition to that the anti symmetric product coding (APC) approach, the LUT size is reduced to half and provides a reduction. When APC approach is combined with the OMS technique, the two’s complement operations could be simplified since the input address and LUT output could always be transformed into odd integers, and thus reduces the LUT size to one fourth of the conventional LUT. The proposed LUT multipliers for word size L = W = 5 and 6 bits are coded in VHDL and synthesized in Xilinx ISE 12.2i. The proposed LUT design for small input sizes can be used for efficient implementation of high-precision multiplication by input operand decomposition. Memory-based computing is well suited for many DSP algorithms, which involve multiplication with a fixed set of coefficients. The proposed LUT-based multiplier involves comparable area and time complexity for a word size of 8 bits, but for higher word sizes, it involves significantly less area and less multiplication time than the CSD based multipliers. For 16-bit and 32-bit word sizes, it offers more than 30% and 50% of saving in area–delay product over the corresponding CSD multipliers.